Current industry approaches to packaging integrated circuits have key deficiencies: first, the packaging approaches currently available are not able to produce passive circuits such as combiners or filters with performance suitable for modern communication systems; and second, these packaging processes result in significant size growth of the chips in all three dimensions. In a typical package, it is necessary for the package to have at least a 1 mm region around the chip in the planar dimensions. In addition, packages with a physical height less than 0.5 mm are difficult to achieve, particularly for parts that require an air cavity above the chip. As a result a semiconductor chip that is 1×1.5 mm in the planar direction and 0.1 mm thick will grow to a packaged part that is at least 3×3.5×0.5 mm, a volume increase of 35× from the bare chip to the packaged chip. This volume can be a key driver in systems such as phased arrays. For example, a 30 GHz phased array with half wavelength element pitch provides a total area of 5×5 mm for each element. While the third axis out of the 5×5 mm plane is not confined, fitting all required parts into the element pitch is a key driver for being able to use a tile based approach in implementing the array. The new approach detailed in the present disclosure solves both of these problems, while also providing improved input/output insertion loss and superior ability to stack packaged parts in the vertical axis.